CS4354-CSZ【PDF 7/24 页】IC DAC 24BIT SRL 14SOIC

收藏本站

您好，
买卖IC网欢迎您。
请登录
免费注册

买卖IC网

Sheet目录1991

3页 4页 5页 6页 [7页]8页 9页 10页 11页

DS895F2

CS4354

Figure 7. De-Emphasis Curve, Fs = 44.1 kHz

Note:

De-emphasis is only available in Single-Speed Mode.

4.5

Internal High-Pass Filter

The CS4354 includes an internal digital high-pass filter. This filter prevents a constant digital offset from cre-

ating a DC voltage on the analog output pins. The filter’s corner frequency is well below the audio band; see

“Combined Digital and On-Chip Analog Filter Characteristics” on page 7 for filter specifications.

4.6

Digital Interface Format

The device accepts audio samples in the industry standard IS format only.

For an illustration of the required relationship between the LRCK, SCLK and SDIN, see Figure 6 on page

14. SDIN is valid on the rising edge of SCLK. For more information about serial audio formats, refer to Cirrus

Logic Application Note AN282: The 2-Channel Serial Audio Interface: A Tutorial, available at

http://www.cirrus.com.

4.7

Internal Power-On Reset

The CS4354 features an internal power-on reset (POR) circuit. This circuit monitors the VA supply and au-

tomatically asserts or releases an internal reset of the DAC’s digital circuitry when the supply reaches de-

fined thresholds (see “Internal Power-On Reset Threshold Voltages” on page 10). No external clocks are

required for the POR circuit to function.

Figure 8. Internal Power-On Reset Circuit

Gain

-10dB

0dB

Frequency

T2 = 15 s

T1=50 s

3.183 kHz

10.61 kHz

Power-On Reset

Circuit

GND

reset

(internal)

发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

*型号	*数量	厂商	批号	封装

添加更多采购

采购需求

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

我的联系方式